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| FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller January 2007 FAN5033 8-Bit Programmable, 2- to 3-Phase, Synchronous Buck Controller Features Selectable 2- or 3-phase operation at up to 1MHz per phase 7.7mV worst-case differential sensing error over temperature Active current balancing between the output phases Power Good and Crowbar blanking supports on-the-fly VID code changes 0.5V to 1.6V output Fully compliant with the Intel(R) VR10 and VR11 specifications Selectable VR10 extended (7-bit) and VR11 (8-bit) VID tables Programmable soft-start ramp Programmable short-circuit protection and latch-off delay Description The FAN5033 device is a multi-phase buck switching regulator controller optimized to convert a 12V input supply to the processor core voltage required by high (R) performance Intel processors. It has an internal 8-bit DAC that converts a digital voltage identification (VID) code, sent from the processor, to set the output voltage between 0.5V and 1.6V in 6.25mV steps. It outputs PWM signals to external MOSFET drivers that drive the switching power MOSFETs. The switching frequency of the design is programmable by a single resistor value. The number of phases can be programmed to support two- or three-phase applications. The FAN5033 also includes programmable no-load offset and droop functions to adjust the output voltage as a function of the load current, as required by the Intel specifications. The FAN5033 provides an accurate and reliable short-circuit protection function with an adjustable over-current set point. The FAN5033 is specified over the commercial temperature range of 0C to +85C and is available in a 32-lead MLP package. Applications Desktop PC/Server processor power supplies for existing and next-generation Intel processors VRM modules Ordering Information Part Number FAN5033MPX Temperature Range 0C to 85C Pb-Free Yes Package Type MLP-32 Packing Method Tape and Reel Quantity 3,000 per Reel Intel is a registered trademark of Intel Corporation. (R) (c) 2007 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Block Diagram VCC RT RAM PADJ FAN5033 UVLO SHUTDOWN & BIAS GND OSCILL ATOR SET EN RESE T PWM1 OD + - CMP Threshold EN - + + CURREN T BALANCING CIRCUI T - + - + - CMP RESE T PWM2 DAC+OV P CSREF CMP RESE T PWM3 + DAC - UV P 2 / 3 - PHASE DRIVER LOGIC - PWRGD DEL AY CROWBAR CURREN T LIMIT SW1 SW2 SW3 NC CSCOM P ILIMI T DEL AY CURREN T LIMIT CIRCUI T + - CSREF CSSUM Z + COM P - PRECISION REFERENCE FBRTN START-UP CONTRO L + - - FB + Boot Control VID DAC VIDSE L DAC BUFF SS VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Figure 1: Block Diagram (c) 2007 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 2 of 39 FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Pin Assignment Figure 2: Pin Assignment Pin Definitions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 Name EN PWRGD FBRTN FB COMP SS DELAY ILIMIT RT RAMPADJ CSREF CSSUM CSCOMP Description Power Supply Enable Input. Analog comparator input with hysteresis. If input voltage is higher than the internal threshold, the controller is enabled. If lower, the controller is disabled. Power Good Output. Open drain output that pulls to GND when the output voltage is outside the proper operating range. Feedback Return. VID DAC and Error Amplifier reference for remote sensing of output voltage. Feedback Input. Error amplifier input for remote sensing of output voltage. A positive internal current source is connected to this pin to allow the output voltage to be offset lower than the DAC voltage. Error Amplifier Output. For loop compensation. Soft-Start Input. An external capacitor connected between this pin and GND sets the soft-start ramp-up time. Delay Timer Input. An external capacitor connected between this pin and GND sets the over-current latch-off delay time, BOOT voltage hold time, EN delay time, and PWRGD delay time. Current Limit Set. An external resistor from this pin to GND sets the current limit threshold of the converter. Frequency Set Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Set Input. An external resistor connected between this pin and the converter input voltage sets the internal PWM ramp. Current Sense Amplifier Positive Input. The voltage on this pin is used as the reference for the current sense amplifier. The Power Good and Crowbar functions are also internally connected to this pin. Current Sense Amplifier Negative Input. Current Sense Amplifier Compensation Output. (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 3 of 39 FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Pin # 14 15 16 17 to 19 Name GND OD NC SW3 to SW1 PWM3 to PWM1 VCC VID7 to VID0 VIDSEL Exposed Paddle Description Ground. All internal biasing and logic output signals of the device are referenced to this ground. Output Disable. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO threshold to disable the external MOSFET drivers. (Also referred to as OD# in the text of this document.) No Connection. This pin is not connected internally. Switching Node Current Balance Inputs. Sense the switching side of the inductor and used to measure the current level in each phase. The SW pins of unused phases should be left open. PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the FAN5109. Connecting the PWM3 output to VCC disables that phase, allowing the FAN5033 to operate as a two-phase controller. Supply Voltage for the Device. Voltage Identification Code Inputs. These digital inputs are connected to the internal DAC and used to program the output voltage. These pins have 1A internal pull-down; so if they are left open, the input state is decoded as logic low. VID Table Select Input. A logic low selects the extended VR10 DAC table and a logic high selects the VR11 DAC table. This pin has a 1A internal pull-down; so if left open, the input state is decoded as logic low. Internally connected to die ground. May be connected to ground or left floating. Connect to ground for lowest package thermal resistance. 20 to 22 23 24 to 31 32 - (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 4 of 39 FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Absolute Maximum Rating Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Unless otherwise specified, all other voltages are referenced to GND. Symbol VCC Supply Voltage FBRTN RAMPADJ, PWM3 SW1 - SW3 Parameter Min. -0.3 -0.3 -0.3 -10 -0.3 0 -65 Typ. Max. +15 +0.3 VCC + 0.3 +25 +5.5 +125 +150 300 260 45 Unit V V V V V C C C C C/W All Other Inputs and Outputs TJ TSTG TL TLI JA Operating Junction Temperature Storage Temperature Lead Soldering Temperature (10 seconds) Lead Infrared Temperature (15 seconds) Thermal Resistance Junction-to-Ambient (1) Note: 1. Junction-to-ambient thermal resistance, JA, is a strong function of PCB material, board thickness, thickness and number of copper planes, number of via used, diameter of via used, available copper surface, and attached heat sink characteristics. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC TA Ambient Temperature Parameter Supply Voltage, VCC to GND Min. 9.6 0 Typ. 12 Max. 14.4 +85 Unit V C (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 5 of 39 FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Electrical Characteristics VCC = 12V, FBRTN = GND, and TA = +25C. The * denotes specifications that apply over the full operating temperature range. Symbol Error Amplifier VCOMP Parameter Output Voltage Range Accuracy Relative to nominal DAC output, referenced to FBRTN. Figure 3 Accuracy Relative to nominal DAC output, referenced to FBRTN. Figure 3 Load Line Droop Accuracy Differential Non-linearity Conditions * VRM11 VID Range: 1.00625V to 1.60000V * Min. 0.5 Typ. Max. 4.0 Unit V VFB -7.7 +7.7 mV VFB(BOOT) During Start-up * 1.092 1.100 1.108 V CSREF-CSCOMP= 80mV Figure 5 VCC =10V to 14V * * * * -78 -1 -80 -82 +1 mV LSB % A A A MHz V/s VFB IFB IFBRTN IO(ERR) GBW(ERR) VCSCOMP tBOOT VIH(VID) VIL(VID) VIH(VID) IIN(VID) Line Regulation Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate CSCOMP Voltage Range BOOT Voltage Hold Time Input Low Voltage Input High Voltage Select VR10 Table Select VR11 Table Input Current, VID Low VID Transition Delay Time No CPU Detection Turn-off Delay Time 0.05 13.5 15.0 70 500 20 25 * -250 2 * * 0.8 0.8 -1 0.4 3.3 0.4 3.3 16.5 95 FB forced to VOUT -3% COMP = FB (2) COMP = FB(2) Relative to CSREF CDELAY = 10nF VIDx, VIDSEL VIDx, VIDSEL VIDSEL Logic Low VIDSEL Logic High VID code change to FB change(2) VID code change to OFF state to PWM going low(2) +250 mV ms V V V V A ns ns VID Inputs and VIDSEL * * 200 200 Oscillator fOSC fPHASE VRT VRAMPADJ IRAMPADJ Frequency Frequency Variation Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range TA = 25C, RT= 200K, 3phase RT =100k to GND VRAMPADJ = VDAC + 2k * (VCC - VDAC) / (RRAMPADJ + 2K) * * * 0.25 -20% 1.9 -50 1 400 2.0 4.50 20% 2.1 +50 50 MHz kHz V mV A (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 6 of 39 FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Electrical Characteristics (Continued) VCC = 12V, FBRTN = GND, and TA = +25C. The * denotes specifications that apply over the full operating temperature range. Symbol Current Sense Amplifier VOS(CSA) IBIAS(CSSUM) IBIAS(CSREF) GBW(CSA) VCSACM ICSCOMP tOC(DELAY) VSW(x)CM RSW(x) ISW(x) ISW(x) VILIMIT IILIMIT Parameter Conditions CSSUM - CSREF Figure 4 Current drawn by CSREF Pin CSSUM = CSCOMP CCSCOMP = 10pF (2) (2) Min. Typ. Max. Unit Offset Voltage Input Bias Current (for CSSUM) Input Current (for CSREF) Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Current Limit Latch-off Delay Time Common Mode Range(2) Input Resistance Input Current Input Current Matching Output Voltage Output Current Maximum Output Current * * * -1.0 -50 -3 10 10 +1.0 +50 +3 mV nA A MHz V/s CSSUM and CSREF * * 0 0.05 1 5 3.2 3.2 V V mA ms CDELAY = 10nF * SW(x) = 0V SW(x) = 0V SW(x) = 0V RILIMT = 143k RILIMT = 143k * VCSREF - VCSCOMP, RILIMT = 143k VCL / IILIMT * * * During Start-up * * * Start-up sequence, EN>950mV, CDELAY = 10nF 12 3.0 1.6 12 800 80 * 60 100 * * * * -600 35 1.6 -5 1.6 Current Balance Circuit +200 50 3.3 65 5.0 +5 1.7 12 1.8 mV k A % V A A 120 10 15 3.75 1.7 15 850 100 1 2 18 4.5 1.8 18 900 120 140 mV mV/A A A V A mV mV A ms Current Limit Comparator VCL Current Limit Threshold Voltage Current Limit Setting Ratio Delay Timer IDELAY IDELAY(CL) VDELAY(TH) Soft-Start I(SS) Enable Input VTH(EN) VHYS(EN) IIN(EN) tDELAY(EN) Threshold Voltage Threshold Hysteresis Enable Input Current Turn-on Delay Output Current Normal Mode Output Current Output Current in Current Limit Threshold Voltage (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 7 of 39 FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Electrical Characteristics (Continued) VCC = 12V, FBRTN = GND, and TA = +25C. The * denotes specifications that apply over the full operating temperature range. Symbol OD Output VOL(ODB) VOH(ODB) Parameter Conditions Min. Typ. Max. Unit Output Voltage Low Output Voltage High IPWM(SINK) = 400A IPWM(SOURCE) = 400A * * 4 160 5 400 mV V Power Good Comparator VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) Under-Voltage Threshold Over-Voltage Threshold Output Low Voltage Relative to Nominal DAC Output Relative to Nominal DAC Output IPWRGD(SINK) = -4mA Start-up sequence VID code Changing VID Code Static VCROWBAR Crowbar Trip Point Crowbar Reset Point Relative to Nominal DAC Output Relative to FBRTN Over-voltage to PWM going low Crowbar Blanking Time VID code Change * * * * * * * * * 100 100 250 100 -300 100 -250 150 200 2 250 200 150 300 250 200 350 -200 200 300 mV mV mV ms s ns mV mV s tPWRGD Power Good Delay Time CDELAY = 10nF Power Good Blanking Time tCROWBAR Crowbar Delay Time VID Code Static * 400 ns PWM Outputs VOL(VRTM) VOH(VRTM) Output Voltage Low Output Voltage High Phase Disable Voltage Input Supply VCC VUVLO VULVOLHYS DC Supply Current UVLO Threshold UVLO Hysteresis EN = Logic HIGH VCC rising * * * 6.5 0.7 8 6.9 0.9 12 7.3 1.1 mA V V IPWM(SINK) = 400A IPWM(SOURCE) = 400A Applicable to PWM3 pins only. Connect this pin to VCC to disable the phase.(3) * * 4 160 5 400 mV V V * VCC -.1 Notes: 1. All limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control. 2. AC specifications guaranteed by design and characterization; not production tested. 3. To operate FAN5033 with fewer than three phases, PWM3 should be connected to VCC to disable this phase. See the "Theory of Operation" section for details. (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 8 of 39 FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Test Diagrams 12 V VCC VIDSEL VID0 VID1 VID2 VID3 VID4 VID5 VID6 8 12 V 100nF 8 Bit Code 23 VCC 1.25 V 20k 100nF EN CSCOMP CSSUM CSREF 13 CSCOMP 39k 12 CSSUM CSA 1k + 11 CSREF FB 1k COMP ILIMIT 250k 10nF 10nF SS DELAY GND FBRTN VID7 SW1 SW2 SW3 + V - 1V 14 GND Figure 3: Closed-Loop Output Voltage Accuracy Figure 4: Current Sense Amplifier VOS 12 V Rt as a function of Oscillator Frequency 62 41 5 COMP 23 VCC 1000 8 4 30 8 1000 10k Rt (k) 4 FB 100 dV + + 13 CSCOMP V 11 CSREF V - V 14 GND 10 0 2000 3000 4000 5000 Oscillator Frequency (kHz) Figure 5: Droop Voltage Accuracy Figure 6: RT Required to Set Oscillator Frequency (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 9 of 39 20 1 17 0 14 7 12 9 11 5 10 4 94 86 79 72 67 62 58 54 51 48 45 43 40 38 www.fairchildsemi.com 24 3 FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Table 1: Output Voltage Programming Codes (extended VR10) ; 0 = logic LOW; 1 = logic HIGH. VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID5 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT (V) OFF OFF OFF OFF 1.09375 1.10000 1.10625 1.11250 1.11875 1.12500 1.13125 1.13750 1.14375 1.15000 1.15625 1.16250 1.16875 1.17500 1.18125 1.18750 1.19375 1.20000 1.20625 1.21250 1.21875 1.22500 1.23125 1.23750 1.24375 1.25000 1.25625 1.26250 1.26875 1.27500 1.28125 1.28750 1.29375 1.30000 1.30625 1.31250 1.31875 1.32500 1.33125 1.33750 1.34375 1.35000 1.35625 1.36250 1.36875 1.37500 1.38125 1.38750 1.39375 1.40000 1.40625 1.41250 1.41875 1.42500 1.43125 1.43750 1.44375 1.45000 1.45625 1.46250 (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 10 of 39 FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Table 1: Continued VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID5 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT (V) 1.46875 1.47500 1.48125 1.48750 1.49375 1.50000 1.50625 1.51250 1.51875 1.52500 1.53125 1.53750 1.54375 1.55000 1.55625 1.56250 1.56875 1.57500 1.58125 1.58750 1.59375 1.60000 0.83125 0.83750 0.84375 0.85000 0.85625 0.86250 0.86875 0.87500 0.88125 0.88750 0.89375 0.90000 0.90625 0.91250 0.91875 0.92500 0.93125 0.93750 0.94375 0.95000 0.95625 0.96250 0.96875 0.97500 0.98125 0.98750 0.99375 1.00000 1.00625 1.01250 1.01875 1.02500 1.03125 1.03750 1.04375 1.05000 1.05625 1.06250 1.06875 1.07500 1.08125 1.08750 (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 11 of 39 FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Table 2: Output Voltage Programming Codes (8-bit) 0 = logic LOW; 1 = logic HIGH. (MSB: VID7, LSB: VID0; 11110001b = F1h) HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Voltage OFF OFF 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 Tolerance HEX 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Voltage 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 Tolerance +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) HEX 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Voltage 0.81250 0.80625 0.8 0.79375 0.7875 0.78125 0.775 0.76875 0.7625 0.75625 0.75 0.74375 0.7375 0.73125 0.725 0.71875 0.7125 0.70625 0.7 0.69375 0.6875 0.68125 0.675 0.66875 0.6625 0.65625 0.65 0.64375 0.6375 0.63125 0.625 0.61875 0.6125 0.60625 0.6 0.59375 0.5875 0.58125 0.575 0.56875 0.5625 0.55625 0.55 0.54375 0.5375 0.53125 0.525 0.51875 0.5125 0.50625 0.5 0.49375 0.4875 0.48125 0.475 0.46875 0.4625 0.45625 0.45 0.44375 0.4375 0.43125 0.425 0.41875 Tolerance Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care HEX C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Voltage 0.4125 0.40625 0.40000 0.39375 0.38750 0.38125 0.37500 0.36875 0.36250 0.35625 0.35000 0.34375 0.33750 0.33125 0.32500 0.31875 0.31250 0.30625 0.30000 0.29375 0.28750 0.28125 0.27500 0.26875 0.26250 0.25625 0.25000 0.24375 0.23750 0.23125 0.22500 0.21875 0.21250 0.20625 0.20000 0.19375 0.18750 0.18125 0.17500 0.16875 0.16250 0.15625 0.15000 0.14375 0.13750 0.13125 0.12500 0.11875 0.11250 0.10625 0.10000 0.09375 0.08750 0.08125 0.07500 0.06875 0.06250 0.05625 0.05000 0.04375 0.03750 0.03125 OFF OFF Tolerance Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 - (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 12 of 39 VTT Optional R20 0 C23 0.1uF S1 R23 R24 R25 R27 R28 R30 R32 R34 R35 680 680 680 680 680 680 680 680 680 R20A VIN R9 10K R10 2.2 32 31 30 29 28 27 26 25 VID0 VID1 VID2 VID3 VID4 VID5 R1 1 EN PWRGD FBRTN FB COMP SS DELAY ILIMIT RT FBRTN 2 3 4 Optional C19 R13 C22 5 6 C21 R12 7 SS 8 COMP ILIMIT C24 18nF R38 110K C26 18nF DELAY R11 0 470pF VT VR 1.21K 30.1K R19 Optional 33pF 10 VID6 VIDSEL RAMPADJ CSREF CSSUM CSCOMP GND OD Optional 10 11 12 13 14 15 16 VCORE 9 NC FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 D5 MMSD4148 SOD-123 VTTA C20 4.7uF DIP20 VIDSEL VID0 VID1VID2VID3VID4VID5VID6VID7 R56 R21 680 ENABLE R22 1K R15 3K VR_READY J2 C25 0.1uF D7 GREEN 1nF ENABLE C27 R52 Optional VID7 VCC PWM1 24 PWM1 23 22 PWM2 21 PWM3 SW1 SW2 SW3 20 19 18 17 R47 R48 R49 10 10 10 PWM1 PWM2 PWM2 PWM3 R59 Optional C37 1uF VIN 10 VCC VIN 20 19 18 17 16 15 14 13 12 11 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VIDSEL 1 2 3 4 5 6 7 8 9 10 Q1 BCW33 D1 MMSZ4678 VR_VSSee R1A Optional Figure 7A: Typical FAN5033 Three-Phase Design, Controller (Contact your Fairchild representative for the latest VR11 reference designs) 13 of 39 VR_VSSdie R5 Optional VR_VSSse R2 0 U1 J1 PWM3 SW1 SW2 SW3 VR_VCCse R3 0 VR_VCCdie R6 R4 10 R31 Optional OD R44 0 OD R50 102K R55 102K R57 102K VR_VCCee R2A Optional GND AGND VCORE +12V R39 267K P3 1 VCORE 1 1 +12V C29 P4 1 GND 1 1 GND P2 1 1 P1 1 1 VCC R40 332K C33 3900pF C35 3300pF R43 CSCOMP 0 C28 Optional CSREF R46 39.2K RT2 100K THERMISTOR 5% 6.8nF R45 0 CSREFA R53 68.1K R7 0 R8 0 www.fairchildsemi.com NOTES : 1. Optional parts are not populated unless otherwise specified ; VIN VIN FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 Q5 FD D8780 D4 MS M D4148 SOD 123 Q9B FD D8780 M MSD4148 SOD 123 Q5B F DD8780 R70 10K U3 4 VC C R74 10K SW2 SW2 Q8 FDD8796 Q10 F DD8796 R75 10K C15 1000pf + C75 560uF + C76 560uF + C77 560uF 6 PGND C14 OD 0.1uF C6 1000pf + C65 560uF PWM L DRV FAN5109 C 67 560uF C69 PWM2 560uF 2 5 + + 3 OD B OOT 1 R54 2.2 SW 7 HDRV SW1 L1 VCORE 0. 6uF/ 27A R29 2.2 Q7 FDD8796 R36 10 CSREFA C 4 BOOT 0.1uF LDR V F AN5109 R71 10K 5 1 R17 2.2 Q3 FDD8796 TP_L1 C13 4.7uF 8 TP_L2 L2 VCORE 300nH/30A R63 2.2 R 67 10 CSREFA SW1 SW 7 C8 22uF/16V Q9 FDD8780 C10 22uF/16V C 12 0.1uF C16 22uF/16V C17 22uF/16V C18 0.1uF HDR V 8 D3 U2 4 VCC C2 4.7uF 6 PGND OD 3 OD PWM1 2 PWM 9 9 VIN +12V + C71 Optional J 3 C73 1200uF/ 16V L4 Jumpe r + + + VIN 1 2 3 4 COM +12V COM +12V COM +12V COM +12V M OLEX_8B 8 7 6 5 Figure 7B: Typical FAN5033 Three-Phase Design, Drivers (Contact your Fairchild representative for the latest VR11 reference designs) 14 of 39 Q4 FDD8780 Q4B FDD8780 R72 10K 8 SW3 SW3 L3 VCORE 0.6uH/ 27A R26 2.2 Q6 FD D8796 + R73 10K C 5 1000pf C64 560uF C66 560uF C68 560uF C 70 560uF + + + R33 10 C FA SRE C3 1 0.1uF 5 R16 2.2 Q2 FDD8796 7 T3 P_L GND C 7 22uF/16V C9 22uF/16V C11 0.1uF D2 M MSD4148 SO D123 C72 1200uF/16V C74 1200uF/16V U4 4 VCC H DRV C1 4.7uF C30 C31 C 32 C34 C36 C39 C40 C41 C42 C43 C 44 C 45 C58 C59 C60 C61 C62 C63 10uF/6.3V 10uF/6.3V 10uF/6. 3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6. 3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/ 6.3V 10uF/ 6.3V 10uF/6.3V 6 PG ND SW OD 3 OD BOOT PWM3 2 PWM LDRV F AN5109 Inside Socket C38 C57 C 56 C54 C53 C52 C51 C50 C49 C48 C 47 C 46 C81 C82 C83 C84 C85 C86 10uF/6.3V 10uF/6.3V 10uF/6. 3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6. 3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/ 6.3V 10uF/ 6.3V 10uF/6.3V 9 Bottom Side Socket Optiona l C87 C88 C 89 C90 C91 C93 C94 C95 C96 C97 C 98 C 99 10uF/6.3V 10uF/6.3V 10uF/6. 3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6.3V 10uF/6. 3V Outside Socket Optional www.fairchildsemi.com FAN5033 -- 8-Bit Programmable 2- to 3-Phase Synchronous Buck Controller Theory of Operation Note: The values shown in this section are for reference only. See the parametric tables for actual values. The FAN5033 is a fixed-frequency PWM controller with multi-phase logic outputs for use in two- and threephase synchronous buck CPU power supplies. It has an internal VID DAC designed to interface directly with Intel's 8-bit VRD/VRM 11 and 7-bit VRD/VRM 10.xcompatible CPUs. Multi-phase operation is required for the high currents and low voltages of today's Intel's microprocessors that can require up to 150A of current. The integrated features of the FAN5033 ensure a stable, high-performance topology for: Balanced currents and thermals between phases High-speed response at the lowest possible switching frequency and output decoupling capacitors Tight load line regulation and accuracy High-current output by allowing up to three-phase designs Reduced output ripple due to multi-phase operation Good PC board layout noise immunity Easily settable and adjustable design parameters with simple component selection Two- to three-phase operation allows optimizing designs for cost/performance and support a wide range of applications START-UP SEQUENCE The FAN5033 start-up sequence is shown in Figure 8. Once the EN and UVLO conditions are met, the DELAY pin goes through one cycle (TD1); after which, the internal oscillator starts. The first two clock cycles are used for phase detection. The soft-start ramp is enabled (TD2), raising the output voltage up to the boot voltage of 1.1V. The boot hold time (TD3) allows the processor VID pins settle to the programmed VID code. After TD3 timing is finished, the output soft-starts, either up or down, to the final VID voltage during TD4. TD5 is the time between the output reaching the VID voltage and the PWRGD being presented to the system. PHASE-DETECTION SEQUENCE During start-up, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the FAN5033 operates as a three-phase PWM controller. For two-phase operation, connect the PWM3 pin to VCC. The PWM logic, which is driven by the master oscillator, directs the phase sequencer and channel detectors. Channel detection occurs during the first two clock cycles after the chip is enabled. During the detection VIDs Invalid period, PWM3 is connected to a 100A sinking current source and two internal voltage comparators check the pin voltage of PWM3 versus a threshold of 3V typical. If the pin is tied to VIN, the pin voltage is above 3V and that phase is disabled and put in a tri-state mode. Otherwise, the internal 100A current source pulls PWM pin below the 3V threshold. After channel detection, the 100A current source is removed. Shorting PWM3 to VCC configures the system for twophase operation. 12V Vin UVLO Threshold Vtt DELAY 0.85V DELAY Threshold 1.0V Vboot =1.1V Vcore = VID Vcore = Vboot SS Vcc (Core) TD1 VRready 50uS Valid TD2 TD3 TD4 TD5 Figure 8: Start-Up Sequence Timing After detection time is complete, the PWM outputs that were not sensed as "pulled high" function as normal PWM outputs. PWM outputs that were sensed as "pulled high" are put into a high-impedance state. The PWM signals are logic-level outputs intended for driving external gate drivers, such as the FAN5109. Since each phase is monitored independently, operation approaching 100% duty cycle is possible. Also, more than one output can be on at the same time to allow overlapping phases. MASTER CLOCK FREQUENCY The clock frequency of the FAN5033 is set with an external resistor connected from the RT pin to ground. The frequency to resistor relationship is shown in Figure 6. To determine the frequency per phase, divide the clock by the number of enabled phases. OUTPUT CURRENT SENSING (See Figure 2) The FAN5033 provides a dedicated current sense amplifier (CSA) to monitor the output current for proper voltage positioning and for current limit detection. It differentially senses the voltage drop across the DCR of the inductors to give the total average current being delivered to the load. This method is inherently more accurate than peak current detection or sampling the voltage across the low-side MOSFETs. The CSA implementation can be configured several ways, depending on the objectives of the system. It can use output inductor DCR sensing without a thermistor, for (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 15 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller lowest cost, or output inductor DCR sensing with a thermistor, for improved accuracy with tracking of inductor temperature. To measure the differential voltage across the output inductors, the positive input of the CSA (CSREF pin) is connected, using equal value resistors, to the output capacitor side of the inductors. The negative input of the CSA (CSSUM pin) is connected, again using equal value resistors, to the MOSFET side of the inductors. The CSA's output (CSCOMP) is a voltage equal to the voltage dropped across the inductors, times the gain of the CSA, and is inversely proportional to the output current. The gain of the CSA is set by connecting an external feedback resistor between the CSA's CSCOMP and CSSUM pins. A capacitor, connected across the resistor, is used to create a low pass filter to remove high-frequency switching effects and to create a RC pole to cancel the zero created by the L/DCR of the inductor. The end result is that the voltage between the CSCOMP and CSREF pins is inversely proportional to the output current (CSCOMP goes negative relative to CSREF as current increases) and the CSA gain sets the ratio of the CSA output voltage change as a function of output current change. This voltage difference is used by the current limit comparator and is also used by the droop amplifier to create the output load line. The CSA is designed to have a low offset input voltage. The sensing gain is determined by external resistors so that it can be extremely accurate. LOAD LINE IMPEDANCE CONTROL The FAN5033 has an internal "Droop Amp" that effectively subtracts the voltage applied between the CSCOMP and CSREF pins from the FB pin voltage of the error amplifier, allowing the output voltage to be varied independent of the DAC setting. A positive voltage on CSCOMP (relative to CSREF) increases the output voltage and a negative voltage decreases it. Since the voltage between the CSA's CSCOMP and CSREF pins is inversely proportional to the output, current causes the output voltage to decrease an amount directly proportional to the increase in output, current, creating a droop or "Load Line." The ratio of output voltage decrease to output current increase is the effective Ro of the power supply and is set by the DC gain of the CSA. CURRENT CONTROL MODE AND THERMAL BALANCE The FAN5033 has individual SW inputs for each phase. They are used to measure the voltage drop across the bottom FETs to determine the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system. This gives good current balance accuracy that takes into account, not only the current, but also the thermal balance between the bottom FETs in each phase. External resistors RSW1 through RSW3 can be placed in series with individual SW inputs to create an intentional current imbalance if desired, such as in cases where one phase has better cooling and can support higher (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 currents. It is best to have the ability to add these resistors in the initial design to ensure that placeholders are provided in the layout. To increase the current in a phase, increase RSW for that phase. Even adding a resistor of a few hundred ohms can make a noticeable increase in current, so use small steps. The amplitude of the internal ramp is set by a resistor connected between the input voltage and the RAMPADJ pin. This method also implements the Voltage Feed Forward function. OUTPUT VOLTAGE DIFFERENTIAL SENSING The FAN5033 uses differential sensing in conjunction with a high accuracy DAC and a low offset error amplifier to maintain a worst-case specification of 7.7mV differential sensing accuracy over its specified operating range. A high gain-bandwidth error amplifier is used for the voltage control loop. The voltage on the FB pin is compared to the DAC voltage to control the output voltage. The FB voltage is also effectively offset by the CSA output voltage for accurately positioning the output voltage as a function of current. The output of the error amplifier is the COMP pin, which is compared to the internal PWM ramps to create the PWM pulse widths. The negative input (FB) is tied to the output sense location with a resistor (RB) and is used for sensing and controlling the output voltage at this point. Additionally a current source is connected internally to the FB pin, which causes a fixed DC current to flow through RB. This current creates a fixed voltage drop (offset voltage) across RB. The offset voltage adds to the sensed output voltage, which causes the error amp to regulate the actual output voltage lower than the programmed VID voltage by this amount. The main loop compensation is incorporated into the feedback by an external network connected between FB and COMP. DELAY TIMER The delay times for the start-up timing sequence are set with a capacitor from the DELAY pin to ground, as described in the Start-Up Sequence section. In UVLO or when EN is logic low, the DELAY pin is held at ground. Once the UVLO and EN are asserted, a 15A current flows out of the DELAY pin to charge CDLY. A comparator, with a threshold of 1.7V, monitors the DELAY pin voltage. The delay time is therefore set by the 15A charging the delay capacitor from 0V to 1.7V. This DELAY pin is used for multiple delay timings (TD1, TD3, and TD5) during start-up. DELAY is also used for timing the current limit latch off as explained in the CURRENT LIMIT section. SOFT-START The soft-start times for the output voltage are set with a capacitor from the SS pin to ground. After TD1 and the phase-detection cycle have been completed, the SS time (TD2 in Figure 8) starts. The SS pin is disconnected from GND and the capacitor is charged up to the 1.1V boot voltage by the SS amplifier, which has a limited output current of 15A. The voltage at the FB pin follows the ramping voltage on the SS pin, limiting www.fairchildsemi.com 16 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller the inrush current during start-up. The soft-start time depends on the value of the boot voltage and CSS. Once the SS voltage is within 100mV of the boot voltage, the boot voltage delay time (TD3) is started. The end of the boot voltage delay time signals the beginning of the second soft-start time (TD4). The SS voltage changes from the boot voltage to the programmed VID DAC voltage (either higher or lower) using the SS amplifier with the limited output current of 15A. The voltage of the FB pin follows the ramping voltage of the SS pin, limiting the inrush current during the transition from the boot voltage to the final DAC voltage. The second soft-start time depends on the boot voltage, the programmed VID DAC voltage, and CSS. If either EN is taken low or VCC drops below UVLO, DELAY and SS are reset to ground to be ready for another soft-start cycle. Figure 9 shows typical start-up waveforms for the FAN5033. starts the latch-off timer. Because the controller continues to operate during the latch-off delay time, if the OC is removed before the 1.7V threshold is reached, the controller returns to normal operation and the DELAY capacitor is reset to GND. The latch-off function can be reset by cycling the supply voltage to the FAN5033 or by toggling the EN pin low for a short time. To disable the short-circuit latch-off function, an external resistor can be placed in parallel with CDLY to prevent the DELAY capacitor from charging up to the 1.7V threshold. The addition of this resistor causes a slight increase in the delay times. During start-up, when the output voltage is below 200mV, a secondary current limit is active. This secondary current limit clamps the internal COMP voltage at the PWM comparators to 1.5V. Typical overcurrent latch-off waveforms are shown in Figure 10. Vcore Vcore VOD# VVRREADY VEN VDELAY VDELAY VPHASE1 Figure 10: Over-Current Latch-off Waveforms Figure 9: Start-up Waveforms CURRENT LIMIT, SHORT-CIRCUIT. AND LATCH-OFF PROTECTION The FAN5033 compares a programmable current limit set point to the voltage from the output of the current sense amplifier. The current limit level is set with the resistor from the ILIMIT pin to ground. During operation, the voltage on ILIMIT is 1.7V. The current through the external resistor is internally scaled to give a current limit threshold of 10mV/A. If the voltage between CSREF and CSCOMP rises above the current limit threshold, the internal current limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. After TD5 has completed, an over-current (OC) event starts a latch-off delay timer. The delay timer uses the DELAY pin timing capacitor. During current limit, the DELAY pin current is reduced to 3.75 A. When the voltage on the delay pin reaches 1.7V, the controller shuts down and latches off. The current limit latch-off delay time is therefore set by the current of 3.75A charging the delay capacitor 1.7V. This delay is four times longer than the delay time during the start-up sequence. If there is a current limit during start-up, the FAN5033 goes through TD1 to TD5 in current limit and (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 DYNAMIC VID The FAN5033 has the ability to dynamically change the VID inputs while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. When a VID input changes state, the FAN5033 detects the change and ignores the DAC inputs for a minimum of 200ns. This time prevents a false code due to logic skew while the eight VID inputs are changing. Additionally, the first VID change initiates the PWRGD and CROWBAR blanking functions for a minimum of 100s to prevent a false PWRGD or CROWBAR event. Each VID change resets the internal timer. POWER GOOD MONITORING The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified based on the VID voltage setting. PWRGD goes low if the output voltage is www.fairchildsemi.com 17 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller outside of the specified range, if the VID DAC inputs are in no CPU mode, or whenever the EN pin is pulled low. PWRGD is blanked during a VID OTF event for a period of ~200s to prevent false signals during the time the output is changing. The PWRGD circuitry also incorporates an initial turn-on delay time (TD5) based on the DELAY timer. Prior to the SS voltage reaching the programmed VID DAC voltage of -100mV, the PWRGD pin is held low. Once the SS pin is within 100mV of the programmed DAC voltage, the capacitor on the DELAY pin begins to charge up. A comparator monitors the DELAY voltage and enables PWRGD when the voltage reaches 1.7V. The PWRGD delay time is therefore set by a current of 15A charging a capacitor from 0V to 1.7V. OUTPUT CROWBAR As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 300mV. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output over-voltage is due to a short in the highside MOSFET, this action current-limits the input supply, protecting the microprocessor. OUTPUT ENABLE AND UVLO For the FAN5033 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold and the EN pin must be higher than its 0.85V threshold. This initiates a system start-up sequence. If either UVLO or EN is less than their respective thresholds, the FAN5033 is disabled, which holds the PWM outputs low, discharges the DELAY and SS capacitors, and forces PWRGD and OD# signals low. In the application circuit, the OD# pin should be connected to the OD# inputs of the FAN5009 or FAN5109 drivers. Pulling OD# low disables the drivers such that both DRVH and DRVL are driven low. This turns off the bottom MOSFETs to prevent them from discharging the output capacitors through the output inductors. If the bottom MOSFETs were left on, the output capacitors could ring with the output inductors and produce a negative output voltage to the processor. NTC Resistance versus Temperature Normalized to 25C 1.0 0.8 Resistance (25C = 1) 0.6 0.4 0.2 0.0 25 50 75 Temperature (C) 100 125 Figure 11: Typical NTC Resistance vs. Temperature (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 18 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller Application Section (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 19 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 20 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 21 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 22 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 23 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 24 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 25 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 26 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 27 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 28 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 29 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 30 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 31 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 32 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 33 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 34 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 35 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 36 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller LAYOUT AND COMPONENT PLACEMENT The following guidelines are recommended for optimal performance of a switching regulator in a PC system. General Recommendations For good results, a PCB with at least four layers is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53m at room temperature. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the FAN5033) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the FAN5033 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing in it. The components around the FAN5033 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB and CSSUM pins. The output capacitors should be connected as close as possible to the load (or connector); for example, a microprocessor core, that receives the power. If the load is distributed, the capacitors should also be distributed and be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop, described in the following section. Power Circuitry Recommendations The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (i.e., EMI) and conduction losses in the board. Failure to take proper precautions results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high-energy ringing, and it accommodates the high-current demand with minimal voltage loss. Whenever a power dissipating component, such as a power MOSFET, is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heatsink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers, extending fully under all the power components. Signal Circuitry Recommendations The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. The FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller. (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 37 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller Mechanical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 12. 32-Lead Molded Leadless Package (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 38 of 39 FAN5033 8-Bit Programmable 2 to 3 Phase Synchronous Buck Controller TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM ActiveArrayTM BottomlessTM Build it NowTM CoolFETTM CROSSVOLTTM DOMETM EcoSPARKTM 2 E CMOSTM EnSignaTM (R) FACT FACT Quiet SeriesTM (R) FAST FASTrTM FPSTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM 2 I CTM i-LoTM ImpliedDisconnectTM IntelliMAXTM ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM (R) OPTOLOGIC OPTOPLANARTM PACMANTM POPTM Power247TM PowerEdgeTM PowerSaverTM (R) PowerTrench (R) QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM ScalarPumpTM SerDesTM (R) SILENT SWITCHER SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TCMTM TinyBoostTM TinyBuckTM (R) TinyLogic TINYOPTOTM TinyPowerTM TinyPWMTM TruTranslationTM (R) UHC UniFETTM VCXTM WireTM Across the board. Around the world.TM Programmable Active DroopTM (R) The Power Franchise DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I22 Preliminary No Identification Needed Full Production Obsolete Not In Production (c) 2006 Fairchild Semiconductor 2006 FAN5033 Rev. 1.0.0 www.fairchildsemi.com 39 of 39 |
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